Conventional fabrication of wafers in very large scale integrated circuit production processes involves use of ion implantation, followed by an annealing step. A post-implant anneal is utilized to activate the ion-implanted dopants in the selected active silicon regions. Typical anneal processes take place at 1000.degree. C. in a nitrogen atmosphere.
Laser pulse annealing is another method reportedly used in activating the dopants. Rapidly pulsing the wafer surface to the required temperature is stated to restore the crystal structure of the substrate without causing juncture movement.
As device dimensions in MOS integrated circuits are scaled down, the parasitic resistance of the diffused regions becomes more significant relative to that of other resistances in the circuit, such as the resistance of the inversion layer. This happens because a reduction of the size of device-dimensions by a factor of S results in a proportional reduction of the length of a diffused region, whereas its cross-sectional (thickness.times.width) area is reduced by an amount proportional to the square of S. The parasitic resistance increases thus by a factor of S. This increase adversely affects device operation because ohmic heat dissipation scales linearly with the resistance and is hence augmented by a factor of S as well. Similarly, the RC time delay of the signal propagation within the circuit is multiplied by a factor S. Because of this increase in parasitic resistance, thin films of silicide compounds are used as a way of lowering the sheet resistivities of the diffused regions and the polysilicon lines. Titanium silicide (TiSi.sub.2) is the most promising material for this purpose because it has the lowest bulk resistivity of the transition metal silicides. Additionally, it is relatively easy to form uniform thin films of this material on silicon either by co-deposition or silicidation.
Recently, the self-aligned silicide (or salicide) process has become widely used in MOS technology. After the gate, source, and drain active regions have been formed in the silicon, sidewall spacers are formed adjacent to the polysilicon lines. This is to prevent gate-to-source or gate-to-drain shorting that would otherwise occur by allowing silicide on the source and drain regions to contact silicide on the polysilicon gate. Titanium is then deposited on the wafer and is thermally reacted to form a silicide. In this process, silicide is formed only where the titanium contacts silicon (i.e., on the diffused regions and the polysilicon lines). The unreacted Ti can then be selectively removed from the other areas by using an etching solution of hydrogen peroxide, and ammonium hydroxide, leaving conducting films of silicide only where they are needed. Because the sheet resistivities of the silicided regions are very low, it is possible to connect devices in the circuit over longer distances using silicided polysilicon instead of metal lines. Thus, the silicide acts to some extent as an additional interconnect layer. Since fewer connections are formed by the metallization, the die area devoted to metal lines (and thus the total die area as well) can be reduced, lowering the cost per die.
In current salicide schemes, the Ti is deposited after the source-drain regions have been implanted and annealed. When silicide is formed on these regions, a portion of the heavily doped junction is consumed as the TiSi.sub.2 interface moves into the silicon while the reaction progresses. The amount of silicon consumed (typically 800-1000 Angstroms) is almost comparable to the junction depths of current devices. As the device dimensions shrink, the junction depths must be scaled down accordingly. The diffusion of dopants both laterally and vertically must be controlled to minimize short channel and other undesirable effects. As junction depths are lowered, the variation in the amount of silicon consumed by the silicide makes it increasingly more difficult to achieve proper final junction depth.
With shrinking device geometries, silicidation after defining the active silicon regions in the integrated circuits being produced on a semiconductor wafer is becoming increasingly impractical because of the lack of control of the silicon layer thickness consumed during the silicidation process. The silicides can sometimes extend through the entire active region, thereby shorting the resulting devices.
The present process was developed to provide greater control of the processing requirements involved in the production of silicide, while also reducing the number of process steps required to complete formation of active regions on a silicon wafer substrate. This is accomplished by simultaneously forming silicide and effecting dopant activation by use of laser irradiation.